對 MPU 不是很了解,根據我粗淺的認知,
WATCHDOG TIMER 是 OPTION ,
要啟動它有些條件 & 程式要做,
機能才會被啟動吧?
有錯請指正 
隨附以前找到的 89S52 資料,
節錄 PAGE 9 的一段內容:
Watchdog Timer
(One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations
where the CPU may be subjected to software upsets. The
WDT consists of a 13-bit counter and the Watchdog Timer
Reset (WDTRST) SFR. The WDT is defaulted to disable
from exiting reset. To enable the WDT, a user must write
01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, it will
increment every machine cycle while the oscillator is running.
The WDT timeout period is dependent on the external
clock frequency. There is no way to disable the WDT
except through reset (either hardware reset or WDT overflow
reset). When WDT overflows, it will drive an output
RESET HIGH pulse at the RST pin.
[ 本文章最後由 sz 於 2011-2-28 09:06 編輯 ] |